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| PEMD48; PUMD48 NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k and R1 = 2.2 k, R2 = 47 k Rev. 05 -- 13 April 2010 Product data sheet 1. Product profile 1.1 General description NPN/PNP double Resistor-Equipped Transistors (RET) in small Surface-Mounted Device (SMD) plastic packages. Table 1. Product overview Package NXP PEMD48 PUMD48 SOT666 SOT363 JEITA SC-88 Package configuration ultra small and flat lead very small Type number 1.2 Features and benefits Built-in bias resistors Simplifies circuit design Reduces component count Reduces pick and place costs 1.3 Applications Low current peripheral driver Replacement of general-purpose transistors in digital applications Control IC inputs 1.4 Quick reference data Table 2. Symbol VCEO IO R1 R2/R1 R1 R2/R1 Quick reference data Parameter collector-emitter voltage output current bias resistor 1 (input) bias resistor ratio bias resistor 1 (input) bias resistor ratio Conditions open base Min 33 0.8 1.54 17 Typ 47 1 2.2 21 Max 50 100 61 1.2 2.86 26 k Unit V mA k Per transistor; for the PNP transistor with negative polarity Transistor TR1 (NPN) Transistor TR2 (PNP) NXP Semiconductors PEMD48; PUMD48 NPN/PNP resistor-equipped transistors 2. Pinning information Table 3. Pin 1 2 3 4 5 6 Pinning Description GND (emitter) TR1 input (base) TR1 output (collector) TR2 GND (emitter) TR2 input (base) TR2 output (collector) TR1 1 2 3 TR1 R2 R1 R1 R2 TR2 Simplified outline Graphic symbol PEMD48 (SOT666) 6 5 4 6 5 4 1 2 3 006aaa143 PUMD48 (SOT363) 1 2 3 4 5 6 GND (emitter) TR1 input (base) TR1 output (collector) TR2 GND (emitter) TR2 input (base) TR2 output (collector) TR1 1 2 3 TR1 R2 R1 R1 R2 TR2 6 5 4 6 5 4 1 2 3 006aaa143 3. Ordering information Table 4. Ordering information Package Name PEMD48 PUMD48 SC-88 Description plastic surface-mounted package; 6 leads plastic surface-mounted package; 6 leads Version SOT666 SOT363 Type number 4. Marking Table 5. PEMD48 PUMD48 [1] * = -: made in Hong Kong * = p: made in Hong Kong * = t: made in Malaysia * = W: made in China PEMD48_PUMD48_5 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Marking codes Marking code[1] 48 4*8 Type number Product data sheet Rev. 05 -- 13 April 2010 2 of 12 NXP Semiconductors PEMD48; PUMD48 NPN/PNP resistor-equipped transistors 5. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCBO VCEO VEBO VI Parameter collector-base voltage collector-emitter voltage emitter-base voltage input voltage TR1 positive negative input voltage TR2 positive negative IO ICM Ptot output current peak collector current total power dissipation PEMD48 (SOT666) PUMD48 (SOT363) Per device Ptot total power dissipation PEMD48 (SOT666) PUMD48 (SOT363) Tj Tamb Tstg [1] [2] Conditions open emitter open base open collector Min - Max 50 50 10 +40 -10 +5 -12 100 100 200 200 Unit V V V V V V V mA mA mW mW Per transistor; for the PNP transistor with negative polarity Tamb 25 C [1][2] [1] - Tamb 25 C [1][2] [1] -65 -65 300 300 150 +150 +150 mW mW C C C junction temperature ambient temperature storage temperature Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. Reflow soldering is the only recommended soldering method. PEMD48_PUMD48_5 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 -- 13 April 2010 3 of 12 NXP Semiconductors PEMD48; PUMD48 NPN/PNP resistor-equipped transistors 6. Thermal characteristics Table 7. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient PEMD48 (SOT666) PUMD48 (SOT363) Per device Rth(j-a) thermal resistance from junction to ambient PEMD48 (SOT666) PUMD48 (SOT363) [1] [2] Conditions Tamb 25 C [1][2] [1] Min Typ Max Unit Per transistor - - 625 625 K/W K/W Tamb 25 C [1][2] [1] - - 416 416 K/W K/W Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. Reflow soldering is the only recommended soldering method. PEMD48_PUMD48_5 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 -- 13 April 2010 4 of 12 NXP Semiconductors PEMD48; PUMD48 NPN/PNP resistor-equipped transistors 7. Characteristics Table 8. Characteristics Tamb = 25 C unless otherwise specified. Symbol ICBO ICEO Parameter collector-base cut-off current collector-emitter cut-off current Conditions VCB = 50 V; IE = 0 A VCE = 30 V; IB = 0 A VCE = 30 V; IB = 0 A; Tj = 150 C Transistor TR1 (NPN) IEBO hFE VCEsat VI(off) VI(on) R1 R2/R1 Cc emitter-base cut-off current DC current gain collector-emitter saturation voltage off-state input voltage on-state input voltage bias resistor 1 (input) bias resistor ratio collector capacitance VCB = 10 V; IE = ie = 0 A; f = 1 MHz VEB = -5 V; IC = 0 A VCE = -5 V; IC = -10 mA IC = -5 mA; IB = -0.25 mA VCE = -5 V; IC = -100 A VCE = -0.3 V; IC = -5 mA VEB = 5 V; IC = 0 A VCE = 5 V; IC = 5 mA IC = 10 mA; IB = 0.5 mA VCE = 5 V; IC = 100 A VCE = 0.3 V; IC = 2 mA 80 3 33 0.8 1.2 1.6 47 1 90 150 0.8 61 1.2 2.5 pF mV V V k A Min Typ Max 100 1 50 Unit nA A A Per transistor; for the PNP transistor with negative polarity Transistor TR2 (PNP) IEBO hFE VCEsat VI(off) VI(on) R1 R2/R1 Cc emitter-base cut-off current DC current gain collector-emitter saturation voltage off-state input voltage on-state input voltage bias resistor 1 (input) bias resistor ratio collector capacitance VCB = -10 V; IE = ie = 0 A; f = 1 MHz 100 -1.1 1.54 17 -0.6 -0.75 2.2 21 -180 -100 -0.5 2.86 26 3 pF mV V V k A PEMD48_PUMD48_5 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 -- 13 April 2010 5 of 12 NXP Semiconductors PEMD48; PUMD48 NPN/PNP resistor-equipped transistors 103 (2) (1) mhc007 10-1 mhc006 hFE VCEsat (V) (3) (1) (2) (3) 102 10 1 10-1 1 10 IC (mA) 102 10-2 10-1 1 10 IC (mA) 102 VCE = 5 V (1) Tamb = 150 C (2) Tamb = 25 C (3) Tamb = -40 C IC/IB = 20 (1) Tamb = 100 C (2) Tamb = 25 C (3) Tamb = -40 C Fig 1. TR1 (NPN): DC current gain as a function of collector current; typical values Fig 2. TR1 (NPN): Collector-emitter saturation voltage as a function of collector current; typical values 10 mhc009 102 VI(on) (V) 10 mhc008 VI(off) (V) (1) 1 (1) (2) (3) 1 (3) (2) 10-1 10-1 1 10 IC (mA) 102 10-1 10-2 10-1 1 IC (mA) 10 VCE = 0.3 V (1) Tamb = -40 C (2) Tamb = 25 C (3) Tamb = 100 C VCE = 5 V (1) Tamb = -40 C (2) Tamb = 25 C (3) Tamb = 100 C Fig 3. TR1 (NPN): On-state input voltage as a function of collector current; typical values Fig 4. TR1 (NPN): Off-state input voltage as a function of collector current; typical values PEMD48_PUMD48_5 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 -- 13 April 2010 6 of 12 NXP Semiconductors PEMD48; PUMD48 NPN/PNP resistor-equipped transistors 103 (1) (2) mhc011 -103 mhc010 hFE VCEsat (mV) 102 (3) -102 10 (1) (3) (2) 1 -10-1 -1 -10 IC (mA) -102 -10 -10-1 -1 -10 IC (mA) -102 VCE = -5 V (1) Tamb = 150 C (2) Tamb = 25 C (3) Tamb = -40 C IC/IB = 20 (1) Tamb = 100 C (2) Tamb = 25 C (3) Tamb = -40 C Fig 5. TR2 (PNP): DC current gain as a function of collector current; typical values Fig 6. TR2 (PNP): Collector-emitter saturation voltage as a function of collector current; typical values mhc013 -104 mhc012 -104 VI(off) (mV) VI(on) (mV) -103 (1) (2) (3) -103 (1) (2) (3) -102 -10-1 -1 -10 IC (mA) -102 -102 -10-2 -10-1 -1 IC (mA) -10 VCE = -0.3 V (1) Tamb = -40 C (2) Tamb = 25 C (3) Tamb = 100 C VCE = -5 V (1) Tamb = -40 C (2) Tamb = 25 C (3) Tamb = 100 C Fig 7. TR2 (PNP): On-state input voltage as a function of collector current; typical values Fig 8. TR2 (PNP): Off-state input voltage as a function of collector current; typical values PEMD48_PUMD48_5 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 -- 13 April 2010 7 of 12 NXP Semiconductors PEMD48; PUMD48 NPN/PNP resistor-equipped transistors 8. Package outline 2.2 1.8 6 0.3 0.1 1.7 1.5 1.3 1.1 pin 1 index 2.2 1.35 2.0 1.15 pin 1 index 5 4 0.45 0.15 1.1 0.8 1.7 1.5 6 5 4 0.6 0.5 1 0.5 1 Dimensions in mm 2 3 0.27 0.17 0.18 0.08 04-11-08 Dimensions in mm 1 0.65 1.3 2 3 0.3 0.2 0.25 0.10 06-03-16 Fig 9. Package outline PEMD48 (SOT666) Fig 10. Package outline PUMD48 (SOT363) 9. Packing information Table 9. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number PEMD48 PUMD48 Package Description SOT666 SOT363 2 mm pitch, 8 mm tape and reel 4 mm pitch, 8 mm tape and reel 4 mm pitch, 8 mm tape and reel; T1 4 mm pitch, 8 mm tape and reel; T2 [1] [2] [3] [2] [3] Packing quantity 3000 -115 -125 4000 -115 8000 -315 10000 -135 -165 For further information and the availability of packing methods, see Section 12. T1: normal taping T2: reverse taping PEMD48_PUMD48_5 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 -- 13 April 2010 8 of 12 NXP Semiconductors PEMD48; PUMD48 NPN/PNP resistor-equipped transistors 10. Revision history Table 10. Revision history Release date 20100413 Data sheet status Product data sheet Change notice Supersedes PEMD48_PUMD48_4 Document ID PEMD48_PUMD48_5 Modifications: * * * * * * * * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 1 "Product profile": amended Table 3 "Pinning": amended Table 8 "Characteristics": Vi(on) redefined to VI(on) on-state input voltage and Vi(off) redefined to VI(off) off-state input voltage Figure 9 and 10: superseded by minimized package outline drawings Section 9 "Packing information": added Section 11 "Legal information": updated Product specification Product specification Product specification Product specification Product specification Preliminary specification PEMD48_PUMD48_3 PEMD48_2 PUMD48_2 PUMD48_1 PEMD48_1 - PEMD48_PUMD48_4 PEMD48_PUMD48_3 PUMD48_2 PUMD48_1 PEMD48_2 PEMD48_1 20040624 20040602 20010201 19990422 20011107 20010924 PEMD48_PUMD48_5 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 -- 13 April 2010 9 of 12 NXP Semiconductors PEMD48; PUMD48 NPN/PNP resistor-equipped transistors 11. Legal information 11.1 Data sheet status Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 11.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer's third party customer(s) (hereinafter both referred to as "Application"). It is customer's sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 11.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or PEMD48_PUMD48_5 11.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 -- 13 April 2010 10 of 12 NXP Semiconductors PEMD48; PUMD48 NPN/PNP resistor-equipped transistors 12. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PEMD48_PUMD48_5 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 -- 13 April 2010 11 of 12 NXP Semiconductors PEMD48; PUMD48 NPN/PNP resistor-equipped transistors 13. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 11 11.1 11.2 11.3 11.4 12 13 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Packing information . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 April 2010 Document identifier: PEMD48_PUMD48_5 |
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